By leveraging a mature 100 nm process to replace sub-16 nm advanced nodes, this technology successfully integrates Ge-based p-FETs with In-based n-FETs featuring nanoscale channel thickness, achieving 2M NAND/mm² and moving toward the target of 20M NAND/mm² (80M Trs/mm²). In addition, this team pioneered a high-performance InWSnO transistor with an ultra-high on/off ratio and low subthreshold swing (SS), demonstrating strong potential for AI and HPC chip applications.

This technology includes both novel material and vertical heterogeneous integration, achieving a high-density logic architecture with 2M NAND/mm² (equivalent 8M Trs/mm²). This work is also the world’s first demonstration of a high-performance indium tungsten tin oxide TFTs, showcasing strong potential for future high-speed, low-power AI chip applications. The related results have been published in top-tier conferences and journals, including the 2025 VLSI Symposium and Advanced Science.

This proposed 3D-IC achieves a world-leading transistor density and enabling logic circuits up to 8M Trs/mm² with a mature 100 nm-node process, instead of advanced several nm-node one. The core technology has been granted a Taiwan patent and is under review for a U.S. patent, demonstrating high commercialization potential. This work also pioneered the InWSnO TFT development, featuring excellent electrical performance, forming a key foundation for advancing next-generation 3D-IC technology.