CPOs integrate the switch chip and modules on the same board, reducing size and distance. This achieves a Nyquist loss of <10dB at 28GHz for 112Gb/s PAM-4 signals. The focus is on a low-power 112Gb/s PAM-4 XSR RX using a 2b/3b TI-ADC. Time-interleaving removes high-speed comparators, allowing a low-speed SAR ADC to be efficient. Replacing some 2-bit ADCs with 3-bit ADCs improves signal alignment. The TX features an unsegmented FFE driver, enhancing bandwidth and reducing power consumption.

This technology introduces an innovative architecture for PAM-4 TRX, achieving power consumption comparable to major IC firms at 7nm using a 28nm process. The TX features a new FFE driver that enhances resolution without requiring multiple driver cells, improving power efficiency. The RX uses TI-ADC to enhance bandwidth. A 2b ADC decodes PAM-4 signals, while 3b ADCs capture error signals for adaptive equalization and CDR locking. A novel asymmetric baud-rate PD further enhances CDR performance.

This technology has multiple patents in the U.S. and Taiwan, indicating strong industrial potential. The commercialized model licenses the TX and RX architecture to IC design houses, maximizing royalty revenue through non-exclusive agreements. Moreover, we can provide the design files and layout for the 112Gb/s PAM-4 TRX chip, validated at 28nm, as high-speed SerDes IP. Other related technologies, such as front-end circuit design, CDR and adaptive equalization algorithms, can also be licensed.