With the progress of AI and IoT, the demand for NVM in edge computing has increased. This project proposes a 3D high-density Via RRAM architecture compatible with advanced FinFET logic process. Featuring full integration to CMOS process, 3D stackability, and high density, the design demonstrates excellent stability, low power consumption, and fast operation through comprehensive device design and electrical validation, making it a promising solution for future embedded memory applications.

The 3D memory has been realized on TSMC 16nm FinFET platform, achieving ultra-high density of 0.4 Gb/mm², surpassing international competitors. Research is ongoing to 7nm node targeting 1 Gb/mm² with hardware fabricated and preliminary electrical analysis. This work was recognized by IEEE VLSI Symposium and displayed in Demo Session. It is extendable to non-volatile logic device, neuromorphic computing, and graphene-based interconnect, as promising solution for high-density memory application.

The 3D Via RRAM is fully compatible to TSMC standard logic process. It has been demonstrated on the 16nm FinFET platform, achieving a density of 0.4 Gb/mm², exceeding international benchmarks with scalability toward 1 Gb/mm² at 7nm node. Featuring high reliability, fast operation, and stable retention, this logic NVM IP is suitable for AI, IoT, and embedded system application. It shows strong potential for technology transfer, offering contribution to next-generation semiconductor technologies.