This technology proposes an algorithm-hardware co-design for low-power, compact semantic segmentation on UAV and satellite platforms. Through pruning and sparsity compression, it reduces memory and computation demand on edge devices. A dedicated hardware accelerator with retiming optimizes data paths, implemented using TSMC 28nm technology as a physical IC operating at 0.65V with 14mW power consumption, extending overall UAV and satellite system runtime by 10%.

This design uses two-stage pruning to compress model parameters to 0.47% of the original, greatly reducing memory access. On the hardware side, retiming and timing borrowing enable lower-voltage operation. Compared to the reference, this design improves power and energy efficiency by 10–40%, reduces area by 10%, and operates reliably at 0.65V under 400MHz. Overall, chip power consumption is reduced by 30%, extending payload system endurance by about 10%.

This design uses two-stage pruning to compress model parameters to 0.47% of the original, greatly reducing memory access. On the hardware side, retiming and timing borrowing enable lower-voltage operation. Compared to the reference, this design improves power and energy efficiency by 10–40%, reduces area by 10%, and operates reliably at 0.65V under 400MHz. Overall, chip power consumption is reduced by 30%, extending payload system endurance by about 10%.